Espressif Systems /ESP32-P4 /SPI0 /SPI_SMEM_DIN_HEX_NUM

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Interpret as SPI_SMEM_DIN_HEX_NUM

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SPI_SMEM_DIN08_NUM 0SPI_SMEM_DIN09_NUM 0SPI_SMEM_DIN10_NUM 0SPI_SMEM_DIN11_NUM 0SPI_SMEM_DIN12_NUM 0SPI_SMEM_DIN13_NUM 0SPI_SMEM_DIN14_NUM 0SPI_SMEM_DIN15_NUM 0SPI_SMEM_DINS_HEX_NUM

Description

MSPI 16x external RAM input timing delay number control register

Fields

SPI_SMEM_DIN08_NUM

the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…

SPI_SMEM_DIN09_NUM

the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…

SPI_SMEM_DIN10_NUM

the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…

SPI_SMEM_DIN11_NUM

the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…

SPI_SMEM_DIN12_NUM

the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…

SPI_SMEM_DIN13_NUM

the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…

SPI_SMEM_DIN14_NUM

the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…

SPI_SMEM_DIN15_NUM

the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…

SPI_SMEM_DINS_HEX_NUM

the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…

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